Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In some CPLDs, configuration data is stored on-chip in non-volatile memory. In other CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
Today, there are new mixed-signal and multi-level simulation languages, which can accurately represent the analog portion of the mixed circuits with behavioral models. Behavioral models are used to describe the analog circuit's behavior on the basis that an input signal to a known system will produce a predictable response signal. Thus, if a function for the input signal vs. output signal is derived, the behavior of the circuit can be predicted without having a full circuit or device level model. Typically, the simulator involves complex mathematical functions having multiple parameters of the input signal necessary to derive the output response.
As FPGAs grow in size, quality on-chip clock distribution becomes increasingly important. Clock skew and clock delay impact device performance and the task of managing clock skew and clock delay becomes more difficult in large devices. Multi-gigabit transceivers (MGTs) are now being included on programmable logic devices (PLDs), such as a field programmable gate array (FPGA). A multi-gigabit transceiver locks to an input data stream through a Clock and Data Recovery (CDR) circuit.
The transceiver includes a phase locked loop (PLL) in the receiver side and in the transmitter side. During normal operation, the receiver PLL automatically locks to incoming data (when present) or to the local reference clock (when data is not present). PLLs may also be used to provide some additional functionality such as frequency synthesis (clock multiplication and clock division) and clock conditioning (duty cycle correction and phase shifting).
Depending on the signal type and functional elements used the PLL can be classified as analogue, discrete, digital or mixed system. However, PLLs are most often implemented using either analog or digital circuitry. Each method has its own advantages. For example, an analog implementation with careful design can produce a PLL with finer timing resolution. Analog implementations can additionally take less silicon area. Conversely, digital implementations offer advantages in noise sensitivity, lower power consumption and jitter performance.
Streamlining the simulation of entire complex system environments, from chip, to package, to board, to connector, to backplane, and back again to chip, has become one of the most urgent needs of designers today. Analog phase locked loop (PLL) performance is verified using analog simulators that are typically too slow to simulate large or complex circuits such as analog phase locked loops. Moreover, faster analog simulators are required to provide accurate simulation of an analog PLL.
It can be seen then that there is a need for a method, apparatus and program storage device for accurately modeling an analog PLL for use in a high speed digital simulator.